The present invention relates to solid-state imaging apparatus, and more particularly relates to the solid-state imaging apparatus in which pixels can be reset at high speed.
A fundamental construction and drive method of a prior-art MOS type solid-state imaging apparatus will first be described by way of FIGS. 1, 2, 3, 4, and 5. FIG. 1 shows a pixel construction used in the MOS solid-state imaging apparatus. What is denoted by a numeral 100 in FIG. 1 is a unit pixel a plurality of which are two-dimensionally arranged into a matrix to acquire image information. The unit pixel 100 includes: a photodiode 101 for effecting photoelectric conversion; an amplification transistor 104 where a photo-generated electric charge occurring at the photodiode 101 is converted into a voltage and is read out as it is amplified for example by means of a pn junction capacitor or gate capacitor; a transfer transistor 102 for transferring the photo-generated electric charge occurring at the photodiode 101 to a gate terminal of the amplification transistor 104; a reset transistor 103 for resetting the gate terminal of the amplification transistor 104 and the photodiode 101; and a select transistor 105 for selecting the pixel so as to transmit an output of the amplification transistor 104 to a vertical signal line 110.
Here, all components but the photodiode 101 are shielded from light.
What is denoted by a numeral 106 is a pixel power supply line for supplying power to all the pixels in common, which is electrically connected to the drain terminal of the amplification transistor 104 and to the drain terminal of the reset transistor 103. 107 is a row reset line for resetting pixels corresponding to one row, which is electrically connected respectively to the gate terminal of the reset transistor 103 of the pixels corresponding to one row. 108 is a row transfer line for transferring the photo-generated electric charge of the pixels corresponding to one row to the gate terminal of the amplification transistor 104 of the respective pixel, which is electrically connected respectively to the gate terminal of each transfer transistor 102 of the pixels corresponding to one row. 109 is a row select line for selecting the pixels corresponding to one row, which is electrically connected respectively to the gate terminal of each select transistor 105 of the pixels corresponding to one row. A photoelectric conversion function, a reset function, a memory function, an amplification/read function, a select function are achieved with such pixel construction.
FIG. 2 typically represents a fundamental construction of the MOS solid-state imaging apparatus. In FIG. 2, a numeral 200 represents a pixel section where unit pixels 100 are two-dimensionally arranged into a matrix that corresponds to pixels P11 to P33. For ease of explanation, the unit pixels 100 in this case are placed side by side into 3 rows by 3 columns. 202 represents a vertical scanning circuit for effecting row selection, which sequentially outputs a vertical scanning signal φ VSR(i) (i=1, 2, 3). 203 represents a vertical selecting section which is to respectively transmit a row select signal φ SE(i) (i=1, 2, 3), a row reset signal φ RS(i) (i=1, 2, 3), and a row transfer signal φ TR(i) (i=1, 2, 3) to the row select line 109, the row reset line 107, and the row transfer line 108 of each pixel P11 to P33 in accordance with the vertical scanning signal φ VSR(i). While in FIG. 2, the lines for transmitting the row select signal φ SE, the row reset signal φ RS, and the row transfer signal φ TR to each row are indicated by one solid line and the outputs of vertical select circuits (MV1, MV2, MV3) of the vertical selecting section 203 are indicated by one solid line for each row, these in actual setting are respectively provided as a number of lines that are independent from each other.
FIG. 3 shows a specific construction of the vertical select circuit (MV1, MV2, MV3) in the vertical selecting section 203. Referring to FIG. 3, 202 is the vertical scanning circuit, and φ SE, φ RS, φ TR are the row select signal, row reset signal, and row transfer signal, respectively. A signal φ SE(i) (i=1, 2, 3) taking AND of the vertical scanning signal φ VSR(i) (i=1, 2, 3) outputted from the vertical scanning circuit 202 and the row select signal φ SE is connected to the row select line 109 in the pixel section 200; a signal φ RS(i) (i=1, 2, 3) taking AND of the vertical scanning signal φ VSR(i) (i=1, 2, 3) and the row reset signal φ RS is connected to the row reset line 107 in the pixel section 200; and a signal φ TR(i) (i=1, 2, 3) taking AND of the vertical scanning signal φ VSR(i) (i=1, 2, 3) and the row transfer signal φ TR is connected to the row transfer line 108 in the pixel section 200.
Referring to FIG. 2, 201 represents a current supply section where current supply ML1, ML2, ML3 provided column by column and the vertical signal line 110 as described in FIG. 1 are respectively connected. A source follower circuit is thereby formed column by column with the amplification transistor 104 of each pixel and the current supply ML1 to ML3. Here the current supply ML1 to ML3 has a function for causing a flow of constant bias current.
Referring to FIG. 2, 204 represents a column processing circuit section where pixel signals outputted from the above described source follower circuits are respectively subjected to correlation double sampling (CDS) by means of column processing circuit CDS1, CDS2, CDS3 provided for each column whereby signal processing is effected for example to remove such offset variance as fixed pattern noise of pixel, and then a result of the signal processing is stored. 205 represents a horizontal scanning circuit for effecting column selection from which horizontal scanning signals φ HSR(j) (j=1, 2, 3) are sequentially outputted. 206 represents a horizontal select switch section where the signal processing result stored at the column processing circuit section 204 is transmitted to the horizontal signal line 207 in accordance with the horizontal scanning signal φ HSR(J) (j=1, 2, 3). 208 represents an amplifier for amplifying and outputting to the outside the signal processing result stored at the column processing circuit 204 which has been transmitted to the horizontal signal line 207.
A drive timing at the time of taking moving picture with thus constructed MOS solid-state imaging apparatus will now be described by way of a timing chart in FIG. 4. When the vertical scanning signal of the first row φ VSR(1) is outputted from the vertical scanning circuit 202, the pixels in the first row are made drivable. More particularly, for the pixels of the first row, the row select signal φ SE may be transmitted to the gate terminal of the select transistor 105 of the first row pixels as the select signal of the first row φ SE(1) through the vertical select circuit MV1 and the row select line 109. Further, the row reset signal φ RS may be transmitted to the gate terminal of the reset transistor 103 of the first row pixels as the reset signal of the first row φ RS(1) through the vertical select circuit MV1 and the row reset line 107. Furthermore, the row transfer signal φ TR may be transmitted to the gate terminal of the transfer transistor 102 of the first row pixels as the transfer signal of the first row φ TR(1) through the vertical select circuit MV1 and the row transfer line 108.
An operation in period Tv will first be described. When the vertical scanning signal φ VSR(1) attains “H” level and then the row select signal φ SE(1) attains “H” level, an output of the amplification transistor 104 may be transmitted onto the vertical signal line 110. In other words, a period for effecting reading of signal and processing of signal is started. Next, when the row reset signal φ RS(1) attains “H” level, the gate terminal of the amplification transistor 104 is reset to the level of a pixel power supply VDD. Next, the row reset signal φ RS(1) is brought to “L” level so that a reset level output outputted from the amplification transistor 104 at this time is sampled at the column processing circuit section 204.
Next, the row transfer signal φ TR(1) is driven to “H” level to transfer photo-generated electric charges accumulated at the photodiode 101 are transferred to the gate terminal of the amplification transistor 104. The row transfer signal φ TR(1) is then brought to “L” level to sample again at the column processing circuit section 204 a signal level output outputted at this time. Subsequently at the column processing circuit section 204, a differential processing between the sampled signal level output and reset level output is performed and the signals after the differential processing are stored respectively at the column processing circuits CDS1, CDS2, and CDS3. The row select signal φ SE(1) is then brought to “L” level whereby the period for effecting signal read and signal processing is ended. When transfer of the photo-generated electric charges accumulated at the photodiode 101 to the gate terminal of the amplification transistor 104 is complete, the photodiode 101 is reset and an accumulation of photo-generated electric charge is started at the photodiode 101.
An operation in period Th will next be described. When the horizontal scanning signal φ HSR(j) (j=1, 2, 3) is sequentially outputted from the horizontal scanning circuit 205, the signals after the differential processing stored at the column processing circuits CDS1, CDS2, CDS3 in the column processing circuit section 204 are sequentially read out onto the horizontal signal line 207 respectively through horizontal select switches MH1, MH2, and MH3 in the horizontal select switch section 206. The signals read out onto the horizontal signal line 207 are amplified at the output amplifier 208 and are outputted to the outside. The signal to be outputted to the outside is shown as Vout in FIG. 4. At this time, a suitable bias current in accordance with signal band is supplied to the output amplifier section 208.
Signals of the pixels corresponding to one row are read out with the above operation. By sequentially effecting this operation from the first row to the third row, signals of all the pixels in the pixel section 200 can be read out. In particular, the pixel signals of the pixels P11 to P33 in the light receiving pixel section 200 are sequentially outputted as Vout from the output amplifier section 208. The periods of the above constitute 1 frame period Tf which in this description, corresponds to an accumulation period of photo-generated electric charge at the photodiode 101.
A description will next be given with respect to case where a still picture is taken with using the solid-state imaging apparatus shown in FIG. 2. In the still picture taking, a mechanical shutter is used to determine an exposure time. In the operation at the time of still picture taking, all pixels are reset (initial reset) in a condition shielded from light by closing the mechanical shutter, and an exposure is subsequently started by opening a first blind of the mechanical shutter. After passage of a desired time, then, light is cut off by closing a second blind of the mechanical shutter so as to end the exposure.
After the end of the exposure, a read operation is rendered.
In transition to the still picture taking from a moving picture taking for example in a live view mode, since the mechanical shutter is always opened at the time of taking moving picture, the mechanical shutter must be closed once and a time lag in the transition is inevitable with the above described method for determining exposure where mechanical shutter is used. In recent years, there is thus provided a method in which an exposure is started by reset operation (initial reset) of the solid-state imaging apparatus to eliminate the time lag in the transition, and the exposure is ended by a mechanical shutter. This method will be referred to hereinafter as first blind electronic shutter. In the first blind electronic shutter operation, it is necessary to perform an initial reset operation and an operation of the mechanical shutter at the same speed so as to match the exposure time between the upper and lower sides of an image. At this time, since mechanical shutter operates at such a high speed as several ms, the initial reset operation must also be performed at a high speed in several ms.
FIG. 5 is a timing chart showing drive timing at the time of still picture taking with using the first blind electronic shutter. When the vertical scanning signal of the first row φ VSR(1) is outputted from the vertical scanning circuit 202, the first row pixels are made drivable. When the vertical scan signal φ VSR(1) attains “H” level and then the row reset signal φ RS(1) attains “H” level, the reset transistors 103 of the pixels corresponding to one row are turned ON. Next, when the row transfer signal φ TR(1) attains “H” level, the photodiodes 101 of the first row attain the power supply voltage VDD whereby the photodiodes 101 are reset and an exposure is started. The second row and after are treated in like manner. After passage of a desired time, then, the exposure is ended by closing the mechanical shutter and signals are read out. The reading of the signals is similar to the signal read operation described in FIG. 4. In the still picture taking, however, since light is cut off at the time of reading, an exposure is not started even after the transferring of photo-generated electric charge is ended.
At the time of initial reset in first blind electronic shutter operation, while the initial reset operation is rendered as shown in FIG. 5 as the reset operation alone is sequentially effected on each row, an initial reset period becomes longer when the number of rows is increased with an increase in the number of pixels; it becomes impossible to meet the mechanical shutter operation.
To make the initial reset operation correspond to the mechanical shutter operation, therefore, the vertical selecting operation must be rendered at a high speed.
Further, a method has been disclosed in Japanese Patent Application Laid-Open 2005-176105 as the method for performing a high-speed initial reset operation. In the method, a plurality of rows is simultaneously reset and this is repeated to achieve the high-speed initial reset operation.